1. Technical Field
The invention relates to computer networks. More particularly, the invention relates to a synchronizing system, and further relates to means used between two devices transmitting data at different speeds to counteract this speed differential as a buffer in systems that are used for the exchange of information over a computer network, especially with regard to the Gigabit Ethernet protocol (IEEE 802.3, clause 36, 1000BASE-X).
2. Description of the Prior Art
In any circuit interfacing two non-correlated and asynchronous clocks, there exists a non-zero probability of sampling a signal from one system with the clock from the other system while the signal is changing. The result of such a sampling, where set-up and hold times are not met, may be an erroneous output. Unpredictably the output can be logic "1", logic "0", or in a metastable state between "1" and "0." This undefined logic state may be interpreted differently by different receiving devices, and in a general configuration it is able to propagate through the succeeding logic gates.
This metastable state is discussed in L. Marino, General Theory of Metastable Operation, IEEE TRANSACTIONS ON COMPUTERS, Vol. C.30, No. 2, pp. 107-115 (February 1981); T. Chaney et al, Anomalous Behavior of Synchronizer and Arbiter Circuits, IEEE TRANSACTIONS ON COMPUTERS, Correspondence, pp. 421-422 (April 1973); and D. Kinniment et al, Circuit Technology in a large computer system, THE RADIO AND ELECTRONIC ENGINEER, Vol. 43, No. 7, pp. 435-441 (July 1973).
The metastable state is potentially unstable and the probability that the output stays in a metastable state decays exponentially with time. All logic families exhibit the metastable operation, when sampling occurs on a transition. However, families with a high-gain bandwidth product are less inclined to exhibit the metastable state than those with a low-gain bandwidth product. The metastable problem is a fundamental problem in digital circuits interfacing asynchronous clocks, and there exists no exact solution to avoid errors. However, the probability of inducing errors due to the metastable operation can be reduced by allowing longer time for the output to settle from the metastable state and by employing high-gain bandwidth product devices.
A method of allowing this output to settle while still receiving data from the source uses what is referred to as an elasticity FIFO, where data is input into the FIFO structure in the incoming clock, and output several unit times later with the outgoing clock. The FIFO acronym refers to "First In First Out", meaning that each datum is output in the order it was received.
In Fiber Channel and Gigabit Ethernet (IEEE 802.3, clause 36, 1000BASE-X, the serial data stream runs continuously and the transmit and receive clock frequencies may differ by as much as 200 parts per million (ppm). The result is that over time, the FIFO that is used to cross this clock boundary reaches a full or empty position. Accordingly, some action must be taken to prevent data overrun or underrun.
An elasticity FIFO (see V. Cavanna, Synchronizing System, U.S. Pat. No. 4,873,703 (Oct. 10, 1989)) was used in a Fiber Channel ASIC (Tachyon), manufactured by Hewlett-Packard Company of Palo Alto, Calif. In the Cavanna design, the solution to adding/deleting entries from the FIFO is to put an elasticity FIFO after the protocol decoder. This allows the FIFO to be aware of when it may safely add or remove symbols. Unfortunately, this approach has the disadvantage that a greater share of the circuit's logic is running off of the incoming clock(s). This is an undesirable result, especially in the Ethernet switching market, where removable transceivers are common--and thus there are times when there is no incoming clock. It is also desirable for testability of the chip to have as much circuitry as possible running off a single clock, Also, keeping the circuitry in the receive clock domain small is better design practice since in cases where circuitry is split between multiple clocks, bugs are often introduced by using a signal from one clock domain in the other clock domain.
For both Fiber Channel and Gigabit Ethernet, the defined interface (see ANSI Technical Report TR/X3.18-1997) uses two receive clocks, each 180 degrees out of phase from one another. This dual clocking allows the interface to use slower logic, but introduces many problems as well. The Cavanna design solves these problems by widening the data path to 16 bits and by clocking most logic off one of the receive clocks. This is acceptable for Fiber Channel devices because all transactions are performed in units of 16 or 32 bits. For Gigabit Ethernet, however, the minimum unit is only 8 bits. While implementations have been developed using wider data paths for Gigabit Ethernet, such wider data path adds size and complexity to the design, especially where it is necessary to signal how many bytes of data are valid within a single data unit and when handling corner cases which arise out of this design style.
Another possible solution to the foregoing problem is to generate a 2.times. clock from the incoming receive clocks. This design, however, would be fraught with problems. For example, this design would require a phase locked loop (PLL) circuit to lock on to the receive clocks, where the receive clocks are already the output of another PLL.
It would be advantageous to provide a method and apparatus that prevents data overrun or underrun in a system that exchanges data using such data exchange protocols as the Gigabit Ethernet protocol.